1. Field of the Invention
This invention relates to a frame synchronization circuit for generating a timing signal in synchronism with each frame of data received, and more particularly to a frame synchronization circuit which performs a resynchronization by means of a plurality of detectors for detecting a synchronization code pattern, thereby to achieve high-speed operation and decrease the synchronization establishing time.
2. Description of the Related Art
In a frame synchronization circuit, it is necessary to decrease the synchronization establishing time. Various methods for decreasing this time have been proposed, among which is the immediate shift method, known in the art as a typical method for this purpose. In this method, the phase of a frame synchronization code in data received is compared with that of a frame pulse generated in the reception side. If they are inconsistent, the clock of a frame pulse generating counter, for example, is stopped, thereby immediately shifting the relative phase of the frame synchronization code and the frame pulse. In the next time slot, these phases are compared in the same manner. In the immediate shift method, a sequence of operations, i.e., synchronization detection, phase comparison, and phase shifting, must be completed within one time slot. Hence, when data is transmitted at high speed, such as hundreds of megabits per second, it is difficult to perform these operations within one time slot.
To decrease the synchronization establishing time and to achieve high speed operation, synchronization reset processing by means of detecting frame synchronization codes in parallel from a series of data signals has been proposed, as in Published Unexamined Japanese Patent Applications (PUJPAs) Nos. 50-102206, 63-245032, and 63-107247.
FIG. 1 shows a frame synchronization circuit for performing synchronization reset processing. The circuit comprises a serial/parallel converting circuit 1, a synchronization code detecting circuit 2 constituted by an M number of pattern detectors #1 to #M, a selection signal generating circuit 3, selector 4, a timing control circuit 5 for generating a frame pulse, and a synchronization protecting circuit 6.
The serial/parallel converting circuit 1 has a serial-in/parallel-out shift register (SR) 11 of 2M-1 bits, a parallel-in/parallel-out parallel register (PR) 12 of 2M-1 bits, and a 1/M frequency divider 13. M denotes the number of bits in one block used when data is processed in blocks.
For example, if M=8, the serial/parallel converting circuit 1 converts a series of data (including a frame synchronization code), input into the frame synchronization circuit, to a 15-bit parallel signal. In this case, since the output of the 1/8 frequency divider 13 does not synchronize with the frame synchronization code in the input data, from what parallel output terminals each bit of the frame synchronization code is output is determined depending on the phase of the output from the frequency divider. More specifically, if M=8, eight different signals can be output from the serial/parallel converting circuit 1; that is, the pattern of the frame synchronization code may occupy first to eighth bits, second to ninth bits, . . . or eighth to fifteenth bits of the parallel signal. The output of the serial/parallel converting circuit 1 is supplied to the synchronization code detecting circuit 2, and input to eight pattern detectors #1 to #8. Bit signals constituted by first to eighth bits, second to ninth bits, . . . or eighth to fifteenth bits, are sequentially input to the respective pattern detectors #1 to #8. Each pattern detector detects a predetermined pattern of a frame synchronization code. The outputs of the pattern detectors #1 to #8 are supplied to the selection signal generating circuit 3.
The selection signal generating circuit 3 calculates a logical sum of the outputs of the synchronization pattern detectors #1 to #8 and outputs a synchronization detecting pulse to the synchronization protecting circuit 6. The selection signal generating circuit 3 also generates a selection signal corresponding to the serial number of the pattern detector which detects the frame synchronization code, on the basis of a control signal supplied from the synchronization protecting circuit 6. The selection signal is supplied to the selector 4. The selector 4 calculates a logical product of the 15-bit parallel data output from the serial/parallel converting circuit 1 and the selection signal supplied from the selection signal generating circuit 3. As a result, 8-bit parallel data corresponding to the detected bit position of the pattern of the frame synchronization code is selectively output on the basis of 15-bit parallel data.
The synchronization protecting circuit 6 compares the phase of the synchronization detecting pulse with that of a frame pulse generated by the timing control circuit and performs a synchronization protecting operation. At this time, if the circuit is set in a hunting mode, the counter in the timing control circuit 5 is reset to correct the phase of the frame pulse.
The above-described frame synchronization method of a parallel detection type is advantageous in that the operation rate required for performing synchronization detection, phase comparison, and phase shifting can be 1/M of that in the immediate shift method, and the synchronization reset time is as short as that in the immediate shift method. However, this method has a drawback in that the synchronization code is inevitably large. The drawback becomes more prominent as the number of bits of a frame synchronization code increases.
For example, FIG. 2 shows a frame synchronization code used in a new synchronization network, standardization of which the CCITT (International Telegraph and Telephone Consultative Committee) is proceeding with. The frame synchronization code of a basic signal called STM-1 is constituted by 48 bits. The frame synchronization code of a signal STM-N (N: the number of multiplication) obtained by multiplexing the signal STM-1 is constituted by 48.times.N bits. If the frame synchronization method of a parallel detection type is applied to the new synchronization network, eight synchronization pattern detectors will be required (M=8), since the new synchronization network is usually based on byte processing. Assuming that all of the synchronization codes of STM-16 are to be detected, eight pattern detectors each constituted by 768 bits are required. Thus, the entire circuit is very large. In order to avoid increasing the size of the circuit, circuit integration is required. However, even if the circuit is integrated into an IC chip, the IC chip will inevitably be accompanied by the drawback of a low operation speed due to the delay time caused by the increase of wiring, also resulting in high power consumption.
As described above, although the conventional frame synchronization circuit of a parallel detection type is advantageous in that the re-synchronization can be performed at high rate, it has the drawback that the synchronization code detecting circuit must be large in accordance with the increase in the number of bits of the frame synchronization code, thereby increasing power consumption.